The subject matter of this application is related to the subject matter of commonly-assigned U.S. patent applications having the following serial numbers and titles: Ser. No. 09/052,059, xe2x80x9cFully Recessed Semiconductor Device and Methodxe2x80x9d; and Ser. No. 09/052,060, xe2x80x9cFully Recessed Semiconductor Device and Method for Low Power Applications With Single Wrap Around Buried Drain Regionxe2x80x9d, all concurrently filed herewith.
The subject matter of this invention relates to semiconductor devices and methods of manufacture, and more particularly, to semiconductor devices and methods of manufacture having a trenched floating gate and a trenched control gate.
Conventional semiconductor non-volatile memories, such as read-only memories (ROMs), erasable-programmable ROMs (EPROMs), electrically erasable-programmable ROMs (EEPROMs) and flash EEPROMs are typically constructed using a double-gate structure. FIG. 1 is a cross-sectional view of the device structure of a conventional nonvolatile memory device 100 including a substrate 102 of a semiconductor crystal such as silicon. The device 100 further includes a channel region 104, a source region 106, a drain region 108, a floating gate dielectric layer 110, a floating gate electrode 112, an inter-gate dielectric layer 114, and a control gate electrode 116. The floating gate dielectric layer 110 isolates the floating gate electrode 112 from the underlying substrate 102 while the inter-gate dielectric 114 isolates the control gate electrode 116 from the floating gate electrode 112. As shown in FIG. 1, the floating gate dielectric layer 110, the floating gate electrode 112, the inter-gate dielectric layer 114, and the control gate electrode 116 are all disposed on the surface of the substrate 102.
As semiconductor devices and integrated circuits are scaled down in size, demands for the efficient use of space have increased. Heretofore, conventional semiconductor memories have utilized a double-gate structure in which both gates being formed on the surface of the silicon substrate as shown in FIG. 1. This type of device structure for non-volatile devices is limited to the degree to which active devices can be made smaller in order to increase packing density. Moreover, when the double gates are stacked on top of the substrate surface as shown in FIG. 1, difficulties in the subsequent contact etch process are created due to the uneven and non-uniform topology.
In accordance with the present invention, a semiconductor device for low power applications is fabricated to include a fully recessed cell structure comprising a trenched floating gate and a trenched control gate. The trenched floating gate and the trenched control gate are both formed in a single trench etched into a well junction region formed in a semiconductor substrate. A buried source region and a buried drain region are formed in the well junction region and are laterally separated by the fully recessed trenched gate structure. The lower boundaries of the buried source region and the buried drain region have a depth which is approximately less than the depth of the trench. The upper boundaries of the buried source region and the buried drain region are of approximately the same depth as the top surface of the trenched floating gate. A fully recessed trenched gate structure embodying the principles of the present invention provides a substantially planar topography that improves the packing density and scaleability of the device. Additionally, the present invention provides low substrate current programming and an enhanced erase operation.
In one embodiment of the present invention, a fully recessed trenched gate device structure for a non-volatile semiconductor device includes a trenched floating gate and a trenched control gate both formed in a single trench etched into the semiconductor substrate. The fully recessed cell structure further includes a well junction region. A buried source region and a buried drain region are formed in the well junction region. The trench is formed in the well junction region and laterally separates the buried source and the buried drain regions. The trenched floating gate is electrically isolated from the trench by a trench-to-gate dielectric layer formed on substantially vertical sidewalls and in a bottom surface inside the trench. An inter-gate dielectric layer is formed on the trenched floating gate and electrically isolates the trenched floating gate from the trenched control gate. The trenched control gate is formed on the inter-gate dielectric layer and in a preferred embodiment, has a top surface which is substantially planar with a surface of the substrate.
In one embodiment of the present invention, sidewall dopings of one conductivity type are formed in the semiconductor substrate. The sidewall dopings are immediately contiguous the substantially vertical sidewalls of the trench and the substrate surface. The depth of the sidewall dopings is approximately equal to or greater than the depth of the trenched control gate and partially extend into the buried source and buried drain regions.
In another embodiment of the present invention, an implanted region of one conductivity type is formed in the semiconductor substrate. The implanted region is laterally separated by the trench and is immediately contiguous the substantially vertical sidewalls of the trench, the substrate surface and the upper boundaries of the buried source region and the buried drain region.
In accordance with the present invention, a fully recessed device structure is formed in a semiconductor substrate using an MOS fabrication process according to which a well junction region is formed in the substrate. A trench is then etched into the well junction region. A trench-to-gate insulating layer is formed on substantially vertical sidewalls and on a bottom surface inside the trench. A trenched floating gate is fabricated by first depositing a layer of polysilicon over the substrate and then etching the polysilicon layer. An inter-gate dielectric is then deposited on the trenched floating gate inside the trench to isolate the two gate electrodes. The trenched control gate is formed by first depositing a layer of polysilicon over the substrate and then planarizing the polysilicon layer until it is substantially planar with the substrate surface. Finally, a buried source region and a buried drain region are formed in the well junction region. In one embodiment, sidewall dopings are formed in the substrate and are immediately contiguous the substantially vertical sidewalls of the trench and immediately contiguous the substrate surface.